PURPOSE: To reduce the occupied pattern area of a control signal multiplexing circuit for integration of the circuit, by scanning and selecting control signal inputs of plural channels by one multiplexer and by processing them by a common control signal converting circuit.
CONSTITUTION: Control signal inputs CH 1 ∼CH n of respective channels are latched at the timing of a multiplexer signal by latch circuits 20 1 ∼20 n and are multiplexed by a multiplexer 21 and are led to a control signal converting circuit 23. From this multiplexed signal output A, a rise pulse multiplexed signal B and a fall pulse multiplexed signal C are generated for every channel signal by a control pulse forming circuit 27 and are transmitted to control lines 24 and 25. Meanwhile, a state holding pulse multiplexed signal E is generated by the second control pulse forming circuit 28 and is transmitted to a line 26. This is, the signal output A is converted and processed successively by the common converting circuit 23.