Control signal multiplexing circuit

Abstract

PURPOSE: To reduce the occupied pattern area of a control signal multiplexing circuit for integration of the circuit, by scanning and selecting control signal inputs of plural channels by one multiplexer and by processing them by a common control signal converting circuit. CONSTITUTION: Control signal inputs CH 1 ∼CH n of respective channels are latched at the timing of a multiplexer signal by latch circuits 20 1 ∼20 n and are multiplexed by a multiplexer 21 and are led to a control signal converting circuit 23. From this multiplexed signal output A, a rise pulse multiplexed signal B and a fall pulse multiplexed signal C are generated for every channel signal by a control pulse forming circuit 27 and are transmitted to control lines 24 and 25. Meanwhile, a state holding pulse multiplexed signal E is generated by the second control pulse forming circuit 28 and is transmitted to a line 26. This is, the signal output A is converted and processed successively by the common converting circuit 23. COPYRIGHT: (C)1982,JPO&Japio

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Patent Citations (2)

    Publication numberPublication dateAssigneeTitle
    JP-S54122915-ASeptember 22, 1979Toshiba CorpSignal multiplex circuit
    JP-S553249-AJanuary 11, 1980Fujitsu LtdInformation transmission system

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Cited By (1)

    Publication numberPublication dateAssigneeTitle
    JP-S6432272-AFebruary 02, 1989Mita Industrial Co LtdElectrophotographic recording method