Schedule system for instruction in parallel computer having plural operating devices

Abstract

PURPOSE:To execute instructions in parallel effectively to simplify hardware for parallel instruction execution, by inspecting an instruction sequence to be executed and giving the same identification name to instructions requiring serializing to serialize instructions including the memory access. CONSTITUTION:Plural scalar or vector operation units 16-1-16-N are provided, and instructions executed in units 16-1-16-N are inputted to a part 19 of a shared memory. Instructions of an object program 10 to be inputted to these units 16-1-16-N are fetched successively by an instruction fetch part 11 and are decoded by an instruction decoder 12, and the same ID is given to instructions which use the same memory area. Next, instructions are stacked in corresponding instruction queue stacks 14-1-14-N by an ID-classified instruction stack control part 14, and instructions of queue stacks 14-1-14-N are taken out to units 16-1-16-N by instruction stack taking-out parts 15-1-15-N and are serialized by the register reserve technique of a serializing control part 17 utilizing a register.

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Patent Citations (2)

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Cited By (8)

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    EP-0279231-A2August 24, 1988International Business Machines CorporationProcesseur d'affichage vidéo en mode graphique pour un système d'affichage vidéo à haute performance
    JP-H0316666-B2March 06, 1991Fujitsu Ltd
    JP-H056712-B2January 27, 1993Fujitsu Ltd
    JP-S5991546-AMay 26, 1984Honeywell Inf SystemsCentral processing unit
    JP-S5991547-AMay 26, 1984Honeywell Inf SystemsCollector
    JP-S60120472-AJune 27, 1985Fujitsu LtdVector processing system of multiple loop
    JP-S61100862-AMay 19, 1986Fujitsu LtdSequencing system of instruction
    JP-S6353571-B2October 24, 1988Haneiueru Infuoomeishon Shisutemusu Inc